The packaging of integrated circuit (IC) chips is one of the most important steps in the manufacturing process, contributing significantly to their overall cost, performance and reliability. As semiconductor devices reach higher levels of integration, packaging technologies have become critical. Packaging of the IC chip accounts for a considerable portion of the cost of producing the device, and failure of the package leads to costly yield reduction.
Continued decrease in semiconductor device feature size has led to a significant increase in semiconductor device density, which places increased emphasis on device or package I/O capabilities. The metal connections, which connect the integrated circuit to other circuits or to system components, have therefore become more important and can, with further miniaturization of the semiconductor device, have an increasingly negative impact on circuit performance. One of the approaches taken to solve such packaging problems is to design chips and chip packaging techniques that offer dependable methods of increased interconnecting of chips at a reasonable manufacturing cost. This has led to the development of “flip-chip” semiconductor packages.
A flip-chip package device includes a direct electrical connection of face down (that is, “flipped”) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive solder bump formed in a ball grid array (BGA) on bondpads of the chip. Flip-chip technology is quickly replacing older wire bonding technology that uses face up chips with a wire connected to each pad on the chip. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on aluminum bondpads on the chips, and interconnects the bumps directly to the package media, which are usually ceramic- or plastic-based. The flip-chip is bonded face down to the package medium through the shortest paths. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger, and to more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an array of I/O interconnects, has the advantage of achieving the highest density of interconnection to the device, combined with a very low inductance interconnection to the package.
The bumps of the flip-chip assembly serve several functions. The bumps provide an electrical conductive path from the IC chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate. The bumps also provide part of the mechanical mounting of the chip to the substrate. A spacer is also provided by the bumps, which prevents electrical contact between the chip and the substrate connectors. Furthermore, the bumps also act as a short lead to relieve mechanical strain between the chip and the substrate.
Despite providing numerous advantages, such semiconductor package devices or assemblies are very delicate structures, the design and manufacturing of which creates difficult and unique technical problems. Continual efforts by those working in the art are being undertaken to improve the performance, reliability and useful life of microelectronic assemblies, particularly those using flip-chips. For example, the flip-chip package device can generate a considerable amount of heat during operation that may range from about 25 to 100 watts concentrated in the area of the chip, which usually ranges from 1 to 4 cubic centimeters. Those working in the art are constantly seeking ways to control and manage this concentrated heat generation to avoid failure of the package device due to overheating.
Failure to manage the heat generated by the flip-chip may be very costly. The heat generated from the flip-chip during operation may cause the chip dimensions to change and may result in damage to signals generated by the chip. Furthermore, thermal expansion may cause the chip to curve, bend or crack. These distortions in the chip may result in damage to the electrical connections between the chip and the substrate. Furthermore, the substrate onto which the flip-chip may be mounted can be a single layer structure, or the substrate may comprise two or many more layers of materials. Often these materials tend to be quite diverse in their composition and structure. The coefficient of thermal expansion (CTE) for these different layers may be considerably different and may result in uncontrolled bending or thermally induced substrate surface distortions. Such distortions can cause failure of the flip-chip or other components of the substrate. In particular, in low-k package devices, the delamination at the interface of the copper (or comparable metal) layers and the passivation layer caused by larger CTE mismatches has become a prominent source of device failure.